| Carry Look-ahead adders (CLA) are used in the broad spectrum of applications from electronicsto medical industry. The critical parameters for the designers of CLA are their speed, size and power. CLA are the core of the arithmetic logic units, graphic processing units of the microprocessors and to perform higher bit addition using CLA in these units of the computers, cascaded structures are commonly used. In this kind of structures, for an instance, a 16-bit addition could be performed by connecting four of 4-bit adders in series. The trade-offs of these structuresare, the propagation time of the carry signal is higher and they need more transistors to realize the logic. Increase in the transistor count leads to higher switching activity and higher power dissipation. This research presents new stand-alone design topologies for CLA carry generationcircuits for 1, 2, 4, and 8-bit addition using complementary metal oxide semiconductor technology. These designs have both input and output signals connected on a single net, in a single architecture. They provide better efficiency compared to the cascaded structures. This work presents, the schematics and the layouts of the proposed stand-alone CLA carry generation implementations and reference stand-alone CLA implementations at various CMOS technology nodes. The proposed stand-alone CLA carry generation circuits are evaluated and compared in terms of their transistor implementation and propagation delay with the reference stand-alone CLA circuitswhich have been published. Both analytically and practically the proposed stand-alone CLA carry generation circuits outperform, the reference stand-alone CLA carry generation circuits. Key words: Carry Look-ahead Adder (CLA), Carry Generation Circuits, Propagation Delay, Stand-alone Design Topology, Complementary Metal Oxide Semiconductor (CMOS) and Speed. |